Design of Optimized Fuzzy Logic Controller for Area Minimisation and its FPGA Implementation

Area optimization is one of the important problems in reconfigurable systems. A Field-programmable gate array (FPGA) based optimised Fuzzy Logic Controller(FLC) has been developed for speed control of DC Motor by exploiting the basic features of Fuzzy logic. The aim of the proposed scheme is to reduce the area, as compared with conventional Fuzzy Logic Controller. The area of a design refers to sum of the area space of the circuit components in FPGA. To implement optimised Fuzzy Logic Controller certain modifications have to made, such that its functionality is identical to original design but requires a smaller area. Real time implementation of Optimised FLC and conventional FLC are made on Spartan-3A DSP FPGA (XC3SD1800A) reconfigurable FPGA for the speed control of DC motor. Results shows that area needed to implement the proposed scheme is reduce drastically and while maintaining the same performance.